In semiconductor memory, proper operation of the memory is based on the correct timing of various internal command and clock signals. For example, in writing data to the memory, internal clock signals that clock data block circuitry to provide (e.g. output) input to the write command may need to be provided substantially concurrently with receipt of write data at input circuitry in order for the data block circuitry to properly capture the write data. If the timing of the internal write command signal is not such that the data block circuitry is enabled at the time the data strobe (DQS) signal clocks the data block circuitry to capture the write data at an expected time, incorrect or incomplete write data may be inadvertently captured and written to the memory.
Moreover, as known, a “latency” may be programmed to set a time, typically in numbers of clock periods (tCK), between receipt of a write command by the memory and receipt of the write data at the memory. The latency may be programmed by a user of the memory to accommodate clock signals of different frequencies (i.e., different clock periods). Other examples of commands that may require the correct timing of internal clock signals and the command for proper operation include, for example, read commands and on-die termination enable commands.
Complicating the providing of correctly timed internal clock and command signals is the relatively high frequency of clock signals. For example, clock signals can exceed 1 GHz. Further complicating the matter is that multi-data rate memories may receive data at a rate higher than the clock signal. The timing domains of command and clock signals may need to be crossed in order to maintain proper timing. An example of a multi-data rate memory is one that receives write data at a rate twice that of the clock frequency, such as receiving data synchronized with clock edges of the clock signal.
In one example, a data strobe signal DQS may be used to time receipt of data, and the timing of the command may be received according to timing of an external clock signal. The timing of the DQS signal could be aligned to the external clock rise/fall edges or it could lag/lead the clock-edges by a certain percentage of an external clock signal clock cycle (e.g., tDQSSmin/max variation). For example, in DDR3 architectures, tDQSSmin/max variation may be up to 25% of tCK. Thus, the range of variation of the DQS signal is 0.5*tCK wide from 0.25*tCK earlier than the external clock to 0.25*tCK later than the external clock, adding a further complication to achieving proper timing.
An example conventional approach of timing internal command to enable capture of data via the DQS signal is delaying the write command through delays such that the DQS signal and the write command have the same propagation delay to the input circuitry. However, the propagation delay of the various internal propagation paths can often vary due to process, voltage, and temperature conditions. For DQS and command paths having relatively long propagation delay or additional delay circuitry, the variations due to operating conditions may negatively affect the timing of the internal signals to such a degree that the memory does not operate properly. Additionally, increasing a clock frequency enhances the negatively affected timing, as a margin for error becomes smaller.